Modern server processors feature dozens or hundreds of hardware CPU cores operating on shared DRAM. However, writing high-throughput concurrent software cannot rely solely on high-level language abstractions. At hardware scale, CPUs aggressively reorder instructions, write buffers delay memory visibility, and cache lines bounce between processor sockets.
While traditional mutexes and spinlocks protect critical sections, they suffer from priority inversion, convoying, and massive lock contention under multi-threaded load. High-performance systems software—from the Linux kernel and DPDK to Netty and high-frequency trading engines—relies on lock-free and wait-free synchronization, memory barriers, and atomic operations.
This module deconstructs multi-core concurrency: hardware memory consistency models, the MESI cache coherence protocol, atomic Compare-And-Swap (CAS) loops, the ABA problem, the Michael-Scott lock-free queue, and Read-Copy-Update (RCU) architectures.